16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Chapter 5 Register Description
The following section describes all LAN9217 registers and data ports.
Note 5.1 The LAN9217 host bus interface supports 16-bit bus transfers; internally, all data paths are
32-bits wide. Figure 5.1 describes the memory map with respect to pairs of atomic 16-bit
transactions.
FCh
RESERVED
B4h
EEPROMPort
B0h
ACh
A8h
MACCSRPort
A4h
A0h
50h
4Ch
48h
44h
40h
3Ch
TX Status FIFO PEEK
TX Status FIFO Port
RX Status FIFO PEEK
RX Status FIFO Port
TX Data FIFO Alias Ports
TX Data FIFO Port
24h
20h
1Ch
RX Data FIFO Alias Ports
04h
00h
Base
+
RX Data FIFO Port
Figure 5.1 Memory Map
SMSC LAN9217
Revision 1.5 (07-18-06)
DATA6S9HEET
SMSC [ SMSC CORPORATION ]
