Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
noted above, the host is required to check the READY bit and verify that it is set before attempting
any other reads or writes of the device.
Note 3.7 The host must do only read accesses prior to the ready bit being set.
Once the READY bit is set, the LAN9215 is ready to resume normal operation. At this time the WUPS
field can be cleared.
3.11.2.2
D2 Sleep
In this state, as shown in Table 3.9, all clocks to the MAC and host bus are disabledand the PHY is
placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY
(Mode Control/Status register) must be set. This places the PHY in the Energy Detect mode. The
PM_MODE bits in the PMT_CTRL register must then be set to 10b. Upon setting the PM_MODE bits,
the LAN9215 will enter the D2 sleep state. The READY bit in PMT_CTRL is cleared when entering the
D2 state.
Note 3.8 If carrier is present when this state is entered detection will occur immediately.
If properly enabled via the ED_EN and PME_EN bits, the LAN9215 will assert the PME hardware
signal upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to
a 01b.
Note 3.9 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
setting of PME_EN.
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN9215 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host
is required to check the READY bit and verify that it is set before attempting any other reads or writes
of the device. Before the LAN9215 is fully awake from this state the EDPWRDOWN bit in register 17
of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit
until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9215 is ready to resume
normal operation. At this time the WUPS field can be cleared.
Table 3.9 Power Management States
LAN9215
BLOCK
D0
D1
(WOL)
D2
(NORMAL OPERATION)
(ENERGY DETECT)
PHY
Full ON
Full ON
Full ON
Energy Detect Power-Down
OFF
MAC Power
Management
RX Power Mgmt. Block
On
MAC and Host
Interface
Full ON
Full ON
OFF
OFF
OFF
Internal Clock
Full ON
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
SMSC LAN9215
Revision 1.5 (07-18-06)
DATA3S7HEET
SMSC [ SMSC CORPORATION ]
