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LAN9215-MT-E2 参数 Datasheet PDF下载

LAN9215-MT-E2图片预览
型号: LAN9215-MT-E2
PDF下载: 下载PDF文件 查看货源
内容描述: 高效10/100以太网控制器, HP Auto-MDIX的 [Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1595 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX  
Datasheet  
3.11  
Power Management  
The LAN9215 supports power-down modes to allow applications to minimize power consumption. The  
following sections describe these modes.  
3.11.1  
System Description  
Power is reduced to various modules by disabling the clocks as outlined in Table 3.9, “Power  
Management States,” on page 37. All configuration data is saved when in either of the twolow power  
states. Register contents are not affected unless specifically indicated in the register description.  
3.11.2  
Functional Description  
There is one normal operating power state, D0 and there are two power saving states: D1, and D2.  
Upon entry into either of the two power saving states, only the PMT_CTRL register is accessible for  
read operations. In either of the power saving states the READY bit in the PMT_CTRL register will be  
cleared. Reads of any other addresses are forbidden until the READY bit is set. All writes, with the  
exception of the wakeup write to BYTE_TEST, are also forbidden until the READY bit is set. Only when  
in the D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed.  
Note 3.3 The LAN9215 must always be read at least once after power-up, reset, or upon return from  
a power-saving state, otherwise write operations will not function.  
In system configurations where the PME signal is shared amongst multiple devices, the WUPS field  
within the PMT_CTRL register can be read to determine which LAN9215 device is driving the PME  
signal.  
When the LAN9215 is in a power saving state (D1 or D2), a write cycle to the BYTE_TEST register  
will return the LAN9215 to the D0 state. Table 7.2, “Power Consumption Device and System  
Components,” on page 130 and Table 7.2, “Power Consumption Device and System Components,” on  
page 130, shows the power consumption values for each power state.  
Note 3.4 When the LAN9215 is in a power saving state, a write of any data to the BYTE_TEST  
register will wake-up the device. DO NOT PERFORM WRITES TO OTHER  
ADDRRESSES while the READY bit in the PMT_CTRL register is cleared.  
3.11.2.1  
D1 Sleep  
Power consumption is reduced in this state by disabling clocks to portions of the internal logic as  
shown in Table 3.9. In this mode the clock to the internal PHY and portions of the MAC are still  
operational. This state is entered when the host writes a '01' to the PM_MODE bits in the Power  
Management (PMT_CTRL) register. The READY bit in PMT_CTRL is cleared when entering the D1  
state.  
Wake-up frame and Magic Packet detection are automatically enabled in the D1 state. If properly  
enabled via the WOL_EN and PME_EN bits, the LAN9215 will assert the PME hardware signal upon  
the detection of the wake-up frame or magic packet. The LAN9215 can also assert the host interrupt  
(IRQ) on detection of a wake-up frame or magic packet. Upon detection, the WUPS field in PMT_CTRL  
will be set to a 10b.  
Note 3.5 The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the  
setting of PME_EN.  
Note 3.6 Wake-up frame and Magic Packet detection is automatically enabled when entering the D1  
state. For wake-up frame detection, the wake-up frame filter must be programmed before  
entering the D1 state (see Section 3.5, "Wake-up Frame Detection," on page 26). If used,  
the host interrupt and PME signal must be enabled prior to entering the D1 state.  
A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was  
detected, will return LAN9215 to the D0 state and will reset the PM_MODE field to the D0 state. As  
Revision 1.5 (07-18-06)  
SMSC LAN9215  
DATA3S6HEET