Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
6.7
TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9215 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9215 . Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Note: The “Data Bus” width is 16 bits.
Table 6.8 TX Data FIFO Direct PIO Write Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcycle
tcsl
Write Cycle Time
165
32
13
0
ns
ns
ns
ns
ns
ns
ns
nCS, nWR Assertion Time
tcsh
tasu
tah
nCS, nWR Deassertion Time (see Note below)
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
133
0
tdsu
tdh
7
0
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order. Parameters tcsh and tcsl must be extended using wait states to meet
the tcycle minimum.
Revision 1.5 (07-18-06)
126
SMSC LAN9215
DATASHEET
SMSC [ SMSC CORPORATION ]
