Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
6.6
PIO Writes
PIO writes are used for all LAN9215 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
A[7:1]
nCS, nRD
Data Bus
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 16 bits.
Table 6.7 PIO Write Cycle Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcycle
tcsl
Write Cycle Time
165
32
13
0
ns
ns
ns
ns
ns
ns
ns
nCS, nWR Assertion Time
nCS, nWR Deassertion Time (see Note below)
Address Setup to nCS, nWR Assertion
Address Hold Time
tcsh
tasu
tah
133
0
tdsu
tdh
Data Setup to nCS, nWR Deassertion
Data Hold Time
7
0
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Parameters tcsh and tcsl must be extended using wait states to meet the tcycle minimum.
SMSC LAN9215
125
Revision 1.5 (07-18-06)
DATASHEET
SMSC [ SMSC CORPORATION ]
