Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
When performing a fast-forward, there must be at least 4 DWORDs of data in the RX data FIFO for
the packet being discarded. For less than 4 DWORDs do not use RX_FFWD. In this case data must
be read from the RX data FIFO and discarded using standard PIO read operations.
After initiating a fast-forward operation, do not perform any reads of the RX data FIFO, RX status FIFO,
or the TX status FIFO until the RX_FFWD bit is cleared. Other resources can be accessed during this
time (i.e., any registers and/or the TX data FIFO). After the fast-forward operation has completed and
the RX_FFWD bit has been cleared, a wait time restriction must be observed before reading the TX
or RX status FIFO’s, as specified in Section 6.1.2, "Special Restrictions on Back-to-Back Read Cycles,"
on page 122. Also note that the RX_FFWD will only fast-forward the RX data FIFO, not the RX status
FIFO.
The receiver does not have to be stopped to perform a fast-forward operation.
3.13.1.2
Force Receiver Discard (Receiver Dump)
In addition to the Receive data Fast Forward feature, LAN9215i also implements a receiver "dump"
feature. This feature allows the host processor to flush the entire contents of the RX data and RX
status FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be
returned to their reset state. To perform a receiver dump, the LAN9215i receiver must be halted. Once
the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The
RX_DUMP bit is cleared when the dump is complete. For more information on stopping the receiver,
please refer to Section 3.13.4, "Stopping and Starting the Receiver," on page 60. For more information
on the RX_DUMP bit, please refer to Section 5.3.7, "RX_CFG—Receive Configuration Register," on
page 80.
Revision 1.93 (12-12-07)
58
SMSC LAN9215i
DATASHEET
SMSC [ SMSC CORPORATION ]
