Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
3.12.7
TX Data FIFO Underrun
If the MIL is not operating in store and forward mode, and the host is unable supply data at the
Ethernet line rate, the TX data FIFO can underrun. If a TX underrun occurs, any further data written
to the TX data FIFO for the offending frame (the frame being transmitted during the underrun) will
automatically be discarded and no further data for that frame will be transmitted. TX data FIFO
underrun is not an error condition, and data transmission will resume with the next valid TX command.
In the case of a TX data FIFO underrun, the (TDFU) flag is set and can be used to generate a host
interrupt. A TX data FIFO underrun is also indicated in the TX status word for the underrun frame.
In the case of a TX underrun, the host is still required to write the remainder of the current TX packet
to the LAN9215i. Any remaining data from the underrun frame that is written to the LAN9215i will back-
up in the TX data FIFO (no more data is read until the next TX SOF [start of frame]). As the data backs
up in the TX data FIFO, it will be visible in the TX_FIFO_INF register. In typical Driver usage, software
will write the entire transmit packet to the LAN9215i and check INT_STS and see (from TDFU) that
the underrun has occurred.
Eventually, the driver will recognize the underrun. A '1' must then be written to the TXD_DUMP bit in
the TX_CFG to flush the remaining data in the TX data FIFO (note that TX_ON may be kept on while
flushing the remaining TX data FIFO contents). Once the leftover data from the underrun frame is
purged, the LAN9215i is ready to send new transmit packets. It is advisable to clear the TDFU bit prior
to transmitting any more data (assuming that SF=0) so that subsequent underruns can be detected,
but this is not required by the hardware.
3.12.8
Transmitter Errors
If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation.
TX Error (TXE) will be asserted under the following conditions:
If the actual packet length count does not match the Packet Length field as defined in the TX
command.
Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX
command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do
not match, the Ethernet controller will assert the Transmitter Error (TXE) flag.
Host overrun of the TX data FIFO.
Overrun of the TX status FIFO (unless TXSAO is enabled)
3.12.9
Stopping and Starting the Transmitter
To halt the transmitter, the host must set the TX_STOP bit in the TX_CFG register. The transmitter will
finish sending the current frame (if there is a frame transmission in progress). When the transmitter
has received the TX status for this frame, it will clear the TX_STOP and TX_ON bits, and will pulse
the TXSTOP_INT.
Once stopped, the host can optionally clear the TX status and TX data FIFOs. The host must re-enable
the transmitter by setting the TX_ON bit. If the there are frames pending in the TX data FIFO (i.e., TX
data FIFO was not purged), the transmission will resume with this data.
3.13
RX Data Path Operation
When an Ethernet Packet is received, the MIL first begins to transfer the RX data. This data is loaded
into the RX data FIFO. The RX data FIFO pointers are updated as data is written into the FIFO.
The last transfer from the MIL is the RX status word. The LAN9215i implements a separate FIFO for
the RX status words. The total available RX data and status queued in the RX FIFO can be read from
the RX_FIFO_INF register. The host may read any number of available RX status words before
reading the RX data FIFO.
SMSC LAN9215i
55
Revision 1.93 (12-12-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
