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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
BITS  
DESCRIPTION  
TYPE  
DEFAULT  
13-12  
Threshold Control Bits (TR). These control the transmit threshold values  
the MIL should use. These bits are used when the SF bit is reset. The host  
can program the Transmit threshold by setting these bits. The intent is to  
allow the MIL to transfer data to the final destination only after the threshold  
value is met.  
R/W  
00  
In 10Mbps mode (TTM = 1) the threshold is set as follows:  
[13]  
0
[12]  
0
Threshold (DWORDS)  
012h  
018h  
020h  
028h  
0
1
1
0
1
1
In 100Mbps mode (TTM = 0) the threshold is set by as follows:  
[13]  
0
[12]  
0
Threshold (DWORDS)  
020h  
040h  
080h  
100h  
0
1
1
0
1
1
11-7  
6-5  
Reserved  
RO  
-
PHY Clock Select (PHY_CLK_SEL). This field is used to switch between  
the internal and external MII clocks (RX_CLK and TX_CLK). This field is  
encoded as follows:  
R/W  
00b  
[6] [5]  
MII Clock Source  
---------------------------------------------------  
0
0
1
1
0
1
0
1
Internal PHY  
External MII Port  
Clocks Disabled  
Internal PHY  
Notes:  
„ This field does not control multiplexing of the SMI port or other MII signals.  
„ There are restrictions on the use of this field. Please refer to Section 3.13,  
"MII Interface - External MII Switching," on page 41 for details.  
4
Serial Management Interface Select (SMI_SEL). This bit is used to switch  
the SMI port (MDIO and MDC) between the internal PHY and the external  
MII port. When this bit is cleared to ‘0’, the internal PHY is selected, and all  
SMI transactions will be to the internal PHY. When this bit is set to ‘1’, the  
external MII port is selected, and all SMI transactions will be to the external  
PHY. This bit functions independent of EXT_PHY_EN. When this bit is set,  
the internal MDIO and MDC signals are driven low. When this bit is cleared,  
the external MIDIO signal is tri-stated, and the MDC signal is driven low.  
R/W  
0
Note:  
This bit does not control the multiplexing of other MII signals.  
SMSC LAN9215I  
Revision 1.5 (07-18-06)  
DATA8S1HEET