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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
Table 2.5 System and Power Signals (continued)  
PIN  
NO.  
BUFFER  
TYPE  
NUM  
PINS  
NAME  
SYMBOL  
DESCRIPTION  
100,99  
,98  
General Purpose  
I/O data,  
nLED1 (Speed  
GPIO[2:0]/  
LED[3:1]  
IS/O12/  
OD12  
3
General Purpose I/O data: These  
three general-purpose signals are  
fully programmable as either push-  
pull output, open-drain output or input  
by writing the GPIO_CFG  
configuration register in the CSR’s.  
They are also multiplexed as GP LED  
connections.  
Indicator),  
nLED2 (Link &  
Activity Indicator),  
nLED3 (Full-  
Duplex  
GPIO signals are Schmitt-triggered  
inputs. When configured as LED  
outputs these signals are open-drain.  
Indicator).  
nLED1 (Speed Indicator). This  
signal is driven low when the  
operating speed is 100Mbs, during  
auto-negotiation and when the cable  
is disconnected. This signal is driven  
high only during 10Mbs operation.  
nLED2 (Link & Activity Indicator).  
This signal is driven low (LED on)  
when the LAN9215I detects a valid  
link. This signal is pulsed high (LED  
off) for 80mS whenever transmit or  
receive activity is detected. This  
signal is then driven low again for a  
minimum of 80mS, after which time it  
will repeat the process if TX or RX  
activity is detected. Effectively, LED2  
is activated solid for a link. When  
transmit or receive activity is sensed  
LED2 will flash as an activity  
indicator.  
nLED3 (Full-Duplex Indicator). This  
signal is driven low when the link is  
operating in full-duplex mode.  
PLL Bias: Connect to an external  
12.0K ohm 1.0% resistor to ground.  
Used for the PLL Bias circuit.  
10  
RBIAS  
RBIAS  
AI  
1
This pin must be connected to VDD  
for normal operation.  
9
2
Test Pin  
ATEST  
VREG  
I
1
1
Internal Regulator  
Power  
P
3.3V input for internal voltage  
regulator  
20,28,  
35,  
42,48,  
55,61,  
97  
+3.3V I/O Power  
I/O Ground  
VDD_IO  
P
P
8
+3.3V I/O logic power supply pins  
19,27,  
34,41,  
47,54,  
60,96  
GND_IO  
8
Ground for I/O pins  
81,85,  
89  
+3.3V Analog  
Power  
VDD_A  
VSS_A  
P
P
3
4
+3.3V Analog power supply pins. See  
Note 2.1  
77,80,  
86,88  
Analog Ground  
Ground for analog circuitry  
Revision 1.5 (07-18-06)  
SMSC LAN9215I  
DATA1S8HEET  
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