Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
Table 2.5 System and Power Signals (continued)
PIN
NO.
BUFFER
TYPE
NUM
PINS
NAME
SYMBOL
DESCRIPTION
6
Crystal 1
XTAL1
lclk
1
External 25MHz Crystal Input.
Can also be connected to single-
ended TTL oscillator. If this method is
implemented, XTAL2 should be left
unconnected.
5
Crystal 2
Reset
XTAL2
Oclk
1
1
External 25MHz Crystal output.
95
nRESET
IS
(PU)
Active-low reset input. Resets all
logic and registers within the
LAN9215I. This signal is pulled
high with a weak internal pull-up
resistor. If nRESET is left
unconnected, the LAN9215I will
rely on its internal power-on reset
circuitry
Note:
The LAN9215I must always
be read at least once after
power-up, reset, or upon
return from a power-saving
state or write operations will
not function. See Section
3.12, "Detailed Reset
Description," on page 39 for
additional information
70
Wakeup Indicator
PME
O8/OD8
1
When programmed to do so, is
asserted when the LAN9215I detects
a wake event and is requesting the
system to wake up from the
associated sleep state. The polarity
and buffer type of this signal is
programmable.
Note:
Detection of a Power
Management Event, and
assertion of the PME signal
will not wakeup the
LAN9215I. The LAN9215I
will only wake up when it
detects a host write cycle
(assertion of nCS and
nWR). Although any write to
the LAN9215I, regardless of
the data written, will wake-
up the device when it is in a
power-saving mode, it is
required that the
BYTE_TEST register be
used for this purpose.
SMSC LAN9215I
Revision 1.5 (07-18-06)
DATA1S7HEET
SMSC [ SMSC CORPORATION ]
