Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
5.4.8
FLOW—Flow Control Register
Offset:
8
Attribute:
Size:
R/W
Default Value:
00000000h
32 bits
This register controls the generation and reception of the Control (Pause command) frames by the
MAC’s flow control block. The control frame fields are selected as specified in the 802.3x Specification
and the Pause-Time value from this register is used in the “Pause Time” field of the control frame. In
full-duplex mode the FCBSY bit is set until the control frame is transferred onto the cable. In half-
duplex mode FCBSY is set while back pressure is being asserted. The host has to make sure that the
Busy bit is cleared before writing the register. The Pass Control Frame bit (FCPASS) does not affect
the sending of the frames, including Control Frames, to the Application Interface. The Flow Control
Enable (FCEN) bit enables the receive portion of the Flow Control block.
This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow
control. Software flow control is initiated using the AFC_CFG register.
Note: The LAN9215I will not transmit pause frames or assert back pressure if the transmitter is
disabled.
BITS
DESCRIPTION
31-16
Pause Time (FCPT). This field indicates the value to be used in the PAUSE TIME field in the control
frame. This field must be initialized before full-duplex automatic flow control is enabled.
15-3
2
Reserved
Pass Control Frames (FCPASS). When set, the MAC sets the Packet Filter bit in the Receive packet
status to indicate to the Application that a valid Pause frame has been received. The Application must
accept or discard a received frame based on the Packet Filter control bit. The MAC receives, decodes
and performs the Pause function when a valid Pause frame is received in Full-Duplex mode and when
flow control is enabled (FCE bit set). When reset, the MAC resets the Packet Filter bit in the Receive
packet status.
The MAC always passes the data of all frames it receives (including Flow Control frames) to the
Application. Frames that do not pass Address filtering, as well as frames with errors, are passed to
the Application. The Application must discard or retain the received frame’s data based on the
received frame’s STATUS field. Filtering modes (Promiscuous mode, for example) take precedence
over the FCPASS bit.
1
0
Flow Control Enable (FCEN). When set, enables the MAC Flow Control function. The MAC decodes
all incoming frames for control frames; if it receives a valid control frame (PAUSE command), it
disables the transmitter for a specified time (Decoded pause time x slot time). When reset, the MAC
flow control function is disabled; the MAC does not decode frames for control frames.
Note:
Flow Control is applicable when the MAC is set in Full Duplex Mode. In Half-Duplex mode,
this bit enables the Backpressure function to control the flow of received frames to the MAC.
Flow Control Busy (FCBSY). This bit is set high whenever a pause frame or back pressure is being
transmitted. This bit should read logical 0 before writing to the Flow Control (FLOW) register. During
a transfer of Control Frame, this bit continues to be set, signifying that a frame transmission is in
progress. After the PAUSE control frame’s transmission is complete, the MAC resets to 0.
Notes:
When writing this register the FCBSY bit must always be zero.
Applications must always write a zero to this bit
SMSC LAN9215I
105
Revision 1.5 (07-18-06)
DATASHEET
SMSC [ SMSC CORPORATION ]
