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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
5.4.6  
MII_ACC—MII Access Register  
Offset:  
6
Attribute:  
Size:  
R/W  
Default Value:  
00000000h  
32 bits  
This register is used to control the Management cycles to the PHY.  
BITS  
DESCRIPTION  
31-16  
15-11  
Reserved  
PHY Address: Selects the external or internal PHY based on its address. The internal PHY is set to  
address 00001b.  
10-6  
5-2  
1
MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.  
Reserved  
MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data  
register. If this bit is not set, this will be a read operation, packing the data in the MII data register.  
0
MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete.  
This bit must read a logical 0 before writing to this register and MII data register.  
The LAN driver software must set (1) this bit in order for the LAN9215I to read or write any of the MII  
PHY registers.  
During a MII register access, this bit will be set, signifying a read or write access is in progress. The  
MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The  
MII data register is invalid until the MAC has cleared this bit during a PHY read operation.  
5.4.7  
MII_DATA—MII Data Register  
Offset:  
7
Attribute:  
Size:  
R/W  
Default Value:  
00000000h  
32 bits  
This register contains either the data to be written to the PHY register specified in the MII Access  
Register, or the read data from the PHY register whose index is specified in the MII Access Register.  
BITS  
31-16  
15-0  
DESCRIPTION  
Reserved  
MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to  
be written to the PHY before an MII write operation.  
Revision 1.5 (07-18-06)  
104  
SMSC LAN9215I  
DATASHEET