High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Top Level Interrupt Registers
(System CSRs)
INT_CFG
INT_STS
INT_EN
1588 Time Stamp Interrupt Register
Bit 29 (1588_EVNT)
of INT_STS register
1588_INT_STS_EN
Switch Fabric Interrupt Registers
Bit 28 (SWITCH_INT)
of INT_STS register
SW_IMR
SW_IPR
Buffer Manager Interrupt Registers
Bit 6 (BM)
BM_IMR
of SW_IPR register
BM_IPR
Switch Engine Interrupt Registers
Bit 5 (SWE)
SWE_IMR
of SW_IPR register
SWE_IPR
Port [2,1,0] MAC Interrupt Registers
Bits [2,1,0] (MAC_[2,1,MII])
MAC_IMR_[2,1,MII]
of SW_IPR register
MAC_IPR_[2,1,MII]
Port 2 PHY Interrupt Registers
PHY_INTERRUPT_SOURCE_2
PHY_INTERRUPT_MASK_2
Bit 27 (PHY_INT2)
of INT_STS register
Port 1 PHY Interrupt Registers
PHY_INTERRUPT_SOURCE_1
PHY_INTERRUPT_MASK_1
Bit 26 (PHY_INT1)
of INT_STS register
Power Management Control Register
Bit 17 (PME_INT)
of INT_STS register
PMT_CTRL
GPIO Interrupt Register
Bit 12 (GPIO)
of INT_STS register
GPIO_INT_STS_EN
Figure 5.1 Functional Interrupt Register Hierarchy
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA5S0HEET
SMSC [ SMSC CORPORATION ]
