High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x)
Register #:
Port0: 045Fh
Port1: 085Fh
Port2: 0C5Fh
Size:
32 bits
This register provides a counter of transmitted packets which experienced a late collision. The counter
is cleared upon being read.
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
TX Late Collision
RC
00000000h
Count of transmitted packets that experienced a late collision. This counter
is incremented only in half-duplex operation.
Note:
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Revision 1.2 (04-08-08)
360
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
