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LAN9210 参数 Datasheet PDF下载

LAN9210图片预览
型号: LAN9210
PDF下载: 下载PDF文件 查看货源
内容描述: 外形小巧单芯片以太网控制器与HP Auto-MDIX的 [Small Form Factor Single- Chip Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网
文件页数/大小: 458 页 / 4618 K
品牌: SMSC [ SMSC CORPORATION ]
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface  
Datasheet  
14.4.2.5  
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)  
Index (decimal):  
4
Size:  
16 bits  
This read/write register contains the advertised ability of the Port x PHY and is used in the Auto-  
Negotiation process with the link partner.  
Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD  
command. Refer to Section 10.2.4, "EEPROM Loader," on page 149 for additional information.  
BITS  
DESCRIPTION  
TYPE  
DEFAULT  
15  
Next Page  
R/W  
0b  
This bit determines the advertised next page capability. The LAN9312 is not  
next page capable. Therefore, this bit must always be 0.  
0: PHY does not advertise next page capability  
1: PHY advertises next page capability  
14  
13  
RESERVED  
RO  
-
Remote Fault  
R/W  
0b  
This bit determines if remote fault indication will be advertised to the link  
partner.  
0: Remote fault indication not advertised  
1: Remote fault indication advertised  
12  
11  
RESERVED  
R/W  
R/W  
0b  
Note:  
This bit should be written as 0.  
Asymmetric Pause  
This bit determines the advertised asymmetric pause capability.  
0b  
Note 14.53  
0: No Asymmetric PAUSE toward link partner advertised  
1: Asymmetric PAUSE toward link partner advertised  
10  
9
Symmetric Pause  
R/W  
R/W  
Note 14.53  
Note 14.54  
This bit determines the advertised symmetric pause capability.  
0: No Symmetric PAUSE toward link partner advertised  
1: Symmetric PAUSE toward link partner advertised  
100BASE-T4  
0b  
This bit determines the advertised 100BASE-T4 capability. The LAN9312  
does not support T4 capability. Therefore, this bit must always be 0.  
0: 100BASE-T4 ability not advertised  
1: 100BASE-T4 ability advertised  
8
7
100BASE-X Full Duplex  
R/W  
R/W  
1b  
1b  
This bit determines the advertised 100BASE-X full duplex capability.  
0: 100BASE-X full duplex ability not advertised  
1: 100BASE-X full duplex ability advertised  
100BASE-X Half Duplex  
This bit determines the advertised 100BASE-X half duplex capability.  
0: 100BASE-X half duplex ability not advertised  
1: 100BASE-X half duplex ability advertised  
Revision 1.2 (04-08-08)  
294  
SMSC LAN9312  
DATASHEET  
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