High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.3.7
Host MAC MII Data Register (HMAC_MII_DATA)
Offset:
7h
Size:
32 bits
This read/write register is used in conjunction with the Host MAC MII Access Register
(HMAC_MII_ACC) to access the internal PHY registers. This register contains either the data to be
written to the PHY register specified in the HMAC_MII_ACC Register, or the read data from the PHY
register whose index is specified in the HMAC_MII_ACC Register.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
15:0
RESERVED
MII Data
RO
-
R/W
0000h
This field contains the 16-bit value read from the PHY read operation or the
16-bit data value to be written to the PHY before an MII write operation.
SMSC LAN9312
279
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
