High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
System CSRs Access
Interrupt Support
2.2.6
Host MAC
The Host MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-
compliant node and provides an interface between the Host Bus Interface (HBI) and the Ethernet PHYs
and Switch Fabric. On the front end, the Host MAC interfaces to the HBI via 2 sets of FIFO’s (TX Data
FIFO, TX Status FIFO, RX Data FIFO, RX Status FIFO). The FIFOs are a conduit between the HBI
and the Host MAC through which all transmitted and received data and status information is passed.
An additional bus is used to access the Host MAC CSR’s via the Host MAC CSR Interface Command
Register (MAC_CSR_CMD) and Host MAC CSR Interface Data Register (MAC_CSR_DATA) system
registers.
On the back end, the Host MAC interfaces with the 10/100 Ethernet PHY’s (Virtual PHY, Port 1 PHY,
Port 2 PHY) via an internal SMI (Serial Management Interface) bus. This allows the Host MAC access
to the PHY’s internal registers via the Host MAC MII Access Register (HMAC_MII_ACC) and Host
MAC MII Data Register (HMAC_MII_DATA). The Host MAC interfaces to the Switch Engine Port 0 via
an internal MII (Media Independent Interface) connection allowing for incoming and outgoing Ethernet
packet transfers.
The Host MAC can operate at either 100Mbps or 10Mbps in both half-duplex or full-duplex modes.
When operating in half-duplex mode, the Host MAC complies fully with Section 4 of ISO/IEC 8802-3
(ANSI/IEEE standard) and ANSI/IEEE 802.3 standards. When operating in full-duplex mode, the Host
MAC complies with IEEE 802.3 full-duplex operation standard.
2.2.7
EEPROM Controller/Loader
The EEPROM Controller is an I2C/Microwire master module which interfaces an optional external
EEPROM with the system register bus and the EEPROM Loader. Multiple types (I2C/Microwire) and
sizes of external EEPROMs are supported. Configuration of the EEPROM type and size are
accomplished via the eeprom_type_strap and eeprom_size_strap[1:0] configuration straps respectively.
Various commands are supported for each EEPROM type, allowing for the storage and retrieval of
static data. The I2C interface conforms to the Philips I2C-Bus Specification.
The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet PHYs, and the system
CSRs. The EEPROM Loader provides the automatic loading of configuration settings from the
EEPROM into the LAN9312 at reset. The EEPROM Loader runs upon a pin reset (nRST), power-on
reset (POR), digital reset (DIGITAL_RST bit in the Reset Control Register (RESET_CTL)), or upon the
issuance of a RELOAD command via the EEPROM Command Register (E2P_CMD).
2.2.8
1588 Time Stamp
The IEEE 1588 Time Stamp modules provide hardware support for the IEEE 1588 Precision Time
Protocol (PTP), allowing clock synchronization with remote Ethernet devices, packet time stamping,
and time driven event generation. Time stamping is supported on all ports, with an individual IEEE
1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master
or a slave clock per the IEEE 1588 specification, and the LAN9312 as a whole may function as a
boundary clock.
A 64-bit tunable clock is provided that is used as the time source for all IEEE 1588 time stamp related
functions. The IEEE 1588 Clock/Events block provides IEEE 1588 clock comparison based interrupt
generation and time stamp related GPIO event generation. Two LAN9312 GPIO pins (GPIO[8:9]) can
be used to trigger a time stamp capture when configured as an input, or output a signal from the GPIO
based on an IEEE 1588 clock target compare event when configured as an output. All features of the
IEEE 1588 hardware time stamp unit can be monitored and configured via their respective IEEE 1588
configuration and status registers (CSRs).
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA2S4HEET
SMSC [ SMSC CORPORATION ]
