High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
2.2.1
System Clocks/Reset/PME Controller
A clock module contained within the LAN9312 generates all the system clocks required by the device.
This module interfaces directly with the external 25MHz crystal/oscillator to generate the required clock
divisions for each internal module, with the exception of the 1588 clocks, which are generated in the
1588 Time Stamp Clock/Events module. A 16-bit general purpose timer and 32-bit free-running clock
are provided by this module for general purpose use.
The LAN9312 reset events are categorized as chip-level resets, multi-module resets, and single-
module resets.
A chip-level reset is initiated by assertion of any of the following input events:
Power-On Reset
nRST Pin Reset
A multi-module reset is initiated by assertion of the following:
Digital Reset - DIGITAL_RST (bit 0) in the Reset Control Register (RESET_CTL)
- Resets all LAN9312 sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual
PHY)
Soft Reset - SRST (bit 0) in the Hardware Configuration Register (HW_CFG)
- Resets the HBI, Host MAC, and System CSRs below address 100h
A single-module reset is initiated by assertion of the following:
Port 2 PHY Reset - PHY2_RST (bit 2) in the Reset Control Register (RESET_CTL) or Reset (bit
15) in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
- Resets the Port 2 PHY
Port 1 PHY Reset - PHY1_RST (bit 1) in the Reset Control Register (RESET_CTL) or Reset (bit
15) in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
- Resets the Port 1 PHY
Virtual PHY Reset - VPHY_RST (bit 0) in the Reset Control Register (RESET_CTL), (bit 10) in
the Power Management Control Register (PMT_CTRL), or Reset (bit 15) in the Virtual PHY Basic
Control Register (VPHY_BASIC_CTRL)
- Resets the Virtual PHY
The LAN9312 supports numerous power management and wakeup features. The Port 1 & 2 PHYs
provide general power-down and energy detect power-down modes, which allow a reduction in PHY
power consumption. The Host MAC provides wake-up frame detection and magic packet detection
modes. The LAN9312 can be programmed to issue an external wake signal (PME) via several
methods, including wake on LAN, wake on link status change (energy detect), and magic packet
wakeup. The PME signal is ideal for triggering system power-up using remote Ethernet wakeup events.
2.2.2
System Interrupt Controller
The LAN9312 provides a multi-tier programmable interrupt structure which is controlled by the System
Interrupt Controller. At the top level are the Interrupt Status Register (INT_STS) and Interrupt Enable
Register (INT_EN). These registers aggregate and control all interrupts from the various LAN9312 sub-
modules. The LAN9312 is capable of generating interrupt events from the following:
1588 Time Stamp
Switch Fabric
Ethernet PHYs
GPIOs
Host MAC (FIFOs, power management)
General Purpose Timer
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA2S2HEET
SMSC [ SMSC CORPORATION ]
