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LAN9210 参数 Datasheet PDF下载

LAN9210图片预览
型号: LAN9210
PDF下载: 下载PDF文件 查看货源
内容描述: 外形小巧单芯片以太网控制器与HP Auto-MDIX的 [Small Form Factor Single- Chip Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网
文件页数/大小: 458 页 / 4618 K
品牌: SMSC [ SMSC CORPORATION ]
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface  
Datasheet  
BITS  
DESCRIPTION  
TYPE  
DEFAULT  
3
Flow Control on Multicast Frame (FCMULT)  
R/W  
0b  
When this bit is set, the Host MAC will assert back pressure when the AFC  
level is reached and a multicast frame is received. This field has no function  
in full-duplex mode.  
0: Flow Control on Multicast Frame Disabled  
1: Flow Control on Multicast Frame Enabled  
2
1
0
Flow Control on Broadcast Frame (FCBRD)  
R/W  
R/W  
R/W  
0b  
0b  
0b  
When this bit is set, the Host MAC will assert back pressure when the AFC  
level is reached and a broadcast frame is received. This field has no function  
in full-duplex mode.  
0: Flow Control on Broadcast Frame Disabled  
1: Flow Control on Broadcast Frame Enabled  
Flow Control on Address Decode (FCADD)  
When this bit is set, the Host MAC will assert back pressure when the AFC  
level is reached and a frame addressed to the Host MAC is received. This  
field has no function in full-duplex mode.  
0: Flow Control on Address Decode Disabled  
1: Flow Control on Address Decode Enabled  
Flow Control on Any Frame (FCANY)  
When this bit is set, the Host MAC will assert back pressure, or transmit a  
pause frame when the AFC level is reached and any frame is received.  
Setting this bit enables full-duplex flow control when the Host MAC is  
operating in full-duplex mode.  
When this mode is enabled during half-duplex operation, the Flow Controller  
does not decode the Host MAC address and will send a JAM upon receipt  
of a valid preamble (i.e., immediately at the beginning of the next frame after  
the RX Data FIFO level is reached).  
When this mode is enabled during full-duplex operation, the Flow Controller  
will immediately instruct the Host MAC to send a pause frame when the RX  
Data FIFO level is reached. The MAC will queue the pause frame  
transmission for the next available window.  
Setting this bit overrides bits [3:1] of this register.  
Table 14.2 Backpressure Duration Bit Mapping  
BACKPRESSURE DURATION  
[7:4]  
0h  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
100Mbs Mode  
5uS  
10Mbs Mode  
7.2uS  
10uS  
12.2uS  
15uS  
17.2uS  
25uS  
27.2uS  
50uS  
52.2uS  
100uS  
150uS  
200uS  
102.2uS  
152.2uS  
202.2uS  
Revision 1.2 (04-08-08)  
190  
SMSC LAN9312  
DATASHEET  
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