High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.2.6
Host MAC RX Dropped Frames Counter Register (RX_DROP)
Offset:
0A0h
Size:
32 bits
This register indicates the number of receive frames that have been dropped by the Host MAC.
BITS
DESCRIPTION
RX Dropped Frame Counter (RX_DFC)
This counter is incremented every time a receive frame is dropped by the
Host MAC. RX_DFC is cleared on any read of this register.
TYPE
DEFAULT
31:0
RC
00000000h
Note:
The interrupt RXDFH_INT (bit 23 of the Interrupt Status Register
(INT_STS)) can be issued when this counter passes through its
halfway point (7FFFFFFFh to 80000000h).
Revision 1.2 (04-08-08)
186
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
