High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
BITS
DESCRIPTION
RX Data FIFO Level Interrupt (RDFL)
TYPE
DEFAULT
5
R/WC
0b
This interrupt is generated when the RX Data FIFO reaches the
programmed level in the RX Space Available Level field of the FIFO Level
Interrupt Register (FIFO_INT).
4
3
RX Status FIFO Full Interrupt (RSFF)
R/WC
R/WC
0b
0b
This interrupt is generated when the RX Status FIFO is full.
RX Status FIFO Level Interrupt (RSFL)
This interrupt is generated when the RX Status FIFO reaches the
programmed level in the RX Status Level field of the FIFO Level Interrupt
Register (FIFO_INT).
2:0
RESERVED
RO
-
Revision 1.2 (04-08-08)
176
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
