High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2
System Control and Status Registers
The System CSR’s are directly addressable memory mapped registers with a base address offset
range of 050h to 2DCh. These registers are addressable by the Host via the Host Bus Interface (HBI).
Table 14.1 lists the System CSR’s and their corresponding addresses in order. All system CSR’s are
reset to their default value on the assertion of a chip-level reset.
The System CSR’s can be divided into 9 sub-categories. Each of these sub-categories contains the
System CSR descriptions of the associated registers. The register descriptions are categorized as
follows:
Section 14.2.1, "Interrupts," on page 172
Section 14.2.2, "Host MAC & FIFO’s," on page 180
Section 14.2.3, "GPIO/LED," on page 192
Section 14.2.4, "EEPROM," on page 197
Section 14.2.5, "IEEE 1588," on page 201
Section 14.2.6, "Switch Fabric," on page 229
Section 14.2.7, "PHY Management Interface (PMI)," on page 243
Section 14.2.8, "Virtual PHY," on page 245
Section 14.2.9, "Miscellaneous," on page 259
Table 14.1 System Control and Status Registers
ADDRESS
OFFSET
SYMBOL
REGISTER NAME
ID_REV
IRQ_CFG
050h
054h
058h
05Ch
060h
064h
068h
06Ch
070h
074h
078h
07Ch
080h
084h
088h
08Ch
Chip ID and Revision Register, Section 14.2.9.1
Interrupt Configuration Register, Section 14.2.1.1
Interrupt Status Register, Section 14.2.1.2
Interrupt Enable Register, Section 14.2.1.3
Reserved for Future Use
INT_STS
INT_EN
RESERVED
BYTE_TEST
FIFO_INT
Byte Order Test Register, Section 14.2.9.2
FIFO Level Interrupts Register, Section 14.2.1.4
Receive Configuration Register, Section 14.2.2.1
Transmit Configuration Register, Section 14.2.2.2
Hardware Configuration Register, Section 14.2.9.3
RX Datapath Control Register, Section 14.2.2.3
Receive FIFO Information Register,Section 14.2.2.4
Transmit FIFO Information Register, Section 14.2.2.5
Power Management Control Register, Section 14.2.9.4
Reserved for Future Use
RX_CFG
TX_CFG
HW_CFG
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
PMT_CTRL
RESERVED
GPT_CFG
General Purpose Timer Configuration Register,
Section 14.2.9.5
GPT_CNT
090h
General Purpose Timer Count Register, Section 14.2.9.6
Reserved for Future Use
RESERVED
094h - 098h
Revision 1.2 (04-08-08)
168
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
