High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Chapter 9 Host MAC
9.1
Functional Overview
The Host MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-
compliant node and provides an interface between the Host Bus Interface (HBI) and the Ethernet PHYs
and Switch Fabric. On the front end, the Host MAC interfaces to the HBI via 2 sets of FIFO’s (TX Data
FIFO, TX Status FIFO, RX Data FIFO, RX Status FIFO). An additional bus is used to access the Host
MAC CSR’s via the Host MAC CSR Interface Command Register (MAC_CSR_CMD) and Host MAC
CSR Interface Data Register (MAC_CSR_DATA) system registers.
The receive and transmit FIFO’s allow increased packet buffer storage to the Host MAC. The FIFOs
are a conduit between the HBI and the Host MAC through which all transmitted and received data and
status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the
various transport and OS software stacks reducing and minimizing overrun conditions. Both the Host
MAC and the TX/RX FIFOs have separate receive and transmit data paths.
The Host MAC can store up to 250 Ethernet packets utilizing FIFOs, totaling 16KB, with a packet
granularity of 4 bytes. This memory is shared by the RX and TX blocks and is configurable in terms
of allocation via the Hardware Configuration Register (HW_CFG) register to the ranges described in
Section 9.7.3, "FIFO Memory Allocation Configuration". This depth of buffer storage minimizes or
eliminates receive overruns.
On the back end, the Host MAC interfaces with the 10/100 Ethernet PHY’s (Virtual PHY, Port 1 PHY,
Port 2 PHY) via an internal SMI (Serial Management Interface) bus. This allows the Host MAC access
to the PHY’s internal registers via the Host MAC MII Access Register (HMAC_MII_ACC) and Host
MAC MII Data Register (HMAC_MII_DATA). The Host MAC interfaces to the Switch Engine Port 0 via
an internal MII (Media Independent Interface) connection allowing for incoming and outgoing Ethernet
packet transfers.
The Host MAC can operate at either 100Mbps or 10Mbps in both half-duplex or full-duplex modes.
When operating in half-duplex mode, the Host MAC complies fully with Section 4 of ISO/IEC 8802-3
(ANSI/IEEE standard) and ANSI/IEEE 802.3 standards. When operating in full-duplex mode, the Host
MAC complies with IEEE 802.3 full-duplex operation standard.
The Host MAC provides programmable enhanced features designed to minimize host supervision, bus
utilization, and pre- or post-message processing. These features include the ability to disable retries
after a collision, dynamic Frame Check Sequence (FCS) generation on a frame-by-frame basis,
automatic pad field insertion and deletion to enforce minimum frame size attributes, and automatic
retransmission and detection of collision frames. The Host MAC can sustain transmission or reception
of minimally-sized back-to-back packets at full line speed with an interpacket gap (IPG) of 9.6
microseconds for 10 Mbps and 0.96 microseconds for 100 Mbps.
The primary attributes of the Host MAC are:
Transmit and receive message data encapsulation
Framing (frame boundary delimitation, frame synchronization)
Error detection (physical medium transmission errors)
Media access management
Medium allocation (collision detection, except in full-duplex operation)
Contention resolution (collision handling, except in full-duplex operation)
Flow control during full-duplex mode
Decoding of control frames (PAUSE command) and disabling the transmitter
Generation of control frames
Interface between the Host Bus Interface and the Ethernet PHYs/Switch Fabric.
Revision 1.2 (04-08-08)
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