Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
TABLE OF CONTENTS
Chapter 1
Chapter 2
Chapter 3
3.1
General Description_________________________________________________________________________ 6
Overview __________________________________________________________________________________ 7
Pin Configurations_________________________________________________________________________ 10
Local Bus vs. PCMCIA vs. 68000 Pin Requirements ________________________________________________ 14
Description of Pin Functions ________________________________________________________________ 16
Buffer Symbols _______________________________________________________________________________ 20
Functional Description _____________________________________________________________________ 22
Buffer Memory _______________________________________________________________________________ 23
Interrupt Structure____________________________________________________________________________ 30
Reset Logic___________________________________________________________________________________ 31
Power Down Logic States_______________________________________________________________________ 31
LAN91C96 Power Down States__________________________________________________________________ 32
PCMCIA CONFIGURATION REGISTERS DESCRIPTION ________________________________________ 35
Frame Format in Buffer Memory for Ethernet __________________________________________________ 37
Registers Map in I/O Space __________________________________________________________________ 41
I/O Space Access ______________________________________________________________________________ 41
I/O Space Registers Description _________________________________________________________________ 41
Theory of Operation________________________________________________________________________ 65
Typical Flow of Events for Transmit (Auto Release = 0) _____________________________________________ 67
Typical Flow of Events for Transmit (Auto Release = 1) _____________________________________________ 68
Flow of Events for Receive______________________________________________________________________ 69
Functional Description of the Blocks __________________________________________________________ 79
Memory Management Unit _____________________________________________________________________ 79
Arbiter ______________________________________________________________________________________ 79
Bus Interface _________________________________________________________________________________ 80
Wait State Policy______________________________________________________________________________ 80
Arbitration Considerations _____________________________________________________________________ 81
DMA Block __________________________________________________________________________________ 81
Packet Number FIFOS_________________________________________________________________________ 82
CSMA Block _________________________________________________________________________________ 84
Network Interface_____________________________________________________________________________ 85
10Base-T___________________________________________________________________________________ 86
AUI _______________________________________________________________________________________ 86
Physical Interface ___________________________________________________________________________ 86
Transmit Functions__________________________________________________________________________ 86
Chapter 4
4.1
Chapter 5
5.1
5.2
5.3
5.4
5.5
5.6
Chapter 6
Chapter 7
7.1
7.2
Chapter 8
8.1
8.2
8.3
Chapter 9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.13.1 Manchester Encoding _______________________________________________________________________ 86
9.13.2 Transmit Drivers___________________________________________________________________________ 87
9.13.3 Jabber Function____________________________________________________________________________ 87
SMSC LAN91C965v&3v
Page 3
Rev. 09/10/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
