Non-PCI Single-Chip Full Duplex Ethernet Controller
5.3
Reset Logic
The pins and bits involved in the different reset mechanisms are:
RESET - Input Pin
SRESET - Soft Reset bit in ECOR, or the SRESET bit
SOFT RST - EPH Soft Reset bit in RCR
Table 5.4 – Reset Logic
SAMPLES
LOCAL BUS
MODE
TRIGGERS
EEPROM
READ
RESETS THE FOLLOWING FUNCTIONS
RESET pin
All internal logic
Yes
No
Yes
Yes
ECOR
The Ethernet controller function except for
the bit itself. Setting this bit also lowers
the nIREQ/READY line. When cleared,
the nIREQ/READY line is raised.
Register
SRESET bit
SOFT RST
The Ethernet controller itself except for
No
No
the IA, CONF and BASE registers.
5.4
Power Down Logic States
Tables Table 5.5 and Table 5.6 describe the power down states of the LAN91C96I. The pins and bits
involved in power down are:
1. PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).
2. Pwrdwn bits in ECSR
3. Enable Function bit in ECOR
4. PWRDN - Legacy power down bit in Control Register.
Rev. 11/18/2004
Page 28
SMSC DS – LAN91C96I
DATASHEET
SMSC [ SMSC CORPORATION ]
