Non-PCI Single-Chip Full Duplex Ethernet Controller
Table 5.1 - LAN91C96I Address Space
SIGNALS
USED
nIORD/
nIOWR
LOCAL
BUS
ON-CHIP
DEPTH
WIDTH
Ethernet I/O
space (1)
Y
Y
16 locations
8 or 16
bits
Table 5.2 - Bus Transactions In Local Bus Mode
A0
0
NSBHE
D0-7
Even byte
D8-15
8 BIT MODE
X
-
((nEN16=1)
(16BIT=0))
1
0
X
0
Odd byte
Even byte
-
16 BIT MODE
otherwise
Odd byte
0
1
1
1
0
1
Even byte
-
-
Odd byte
Invalid cycle
16BIT:
CONFIGURATION REGISTER bit 7
CSR register bit 5
IOis8:
nEN16:
8 Bit mode:
pin nEN16
((IOis8 = 1) + (nMIS16 = 1)
5.2
Interrupt Structure
The Ethernet interrupt is conceptually equivalent to the LAN91C94 interrupt line, it is the or function of all
enabled interrupts within the Ethernet core. The enabling, reporting, and clearing of these sources is
controlled by the ECOR register. The interrupt structure is similar for Local Bus modes with the following
exceptions:
Table 5.3 – Interrupt Merging
FUNCTION
Interrupt Output
LOCAL BUS MODE
INTR0-3
Ethernet Interrupt Source
OR function of all interrupt bits specified in the Interrupt Status Register
ANDed with their respective Enable bits
Ethernet Interrupt Enable
Ethernet Interrupt Status Bit
Not Applicable in Local Bus mode
Intr bit in ECSR
SMSC DS – LAN91C96I
Page 27
Rev. 11/18/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
