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LAN91C111-NE 参数 Datasheet PDF下载

LAN91C111-NE图片预览
型号: LAN91C111-NE
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100非PCI以太网单芯片MAC + PHY [10/100 Non-PCI Ethernet Single Chip MAC + PHY]
分类和应用: PC以太网局域网(LAN)标准
文件页数/大小: 142 页 / 1664 K
品牌: SMSC [ SMSC CORPORATION ]
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10/100 Non-PCI Ethernet Single Chip MAC + PHY  
Datasheet  
Table 12.3 EISA 32 Bit Slave Signal Connections (continued)  
EISA BUS  
SIGNAL  
LAN91C111  
SIGNAL  
NOTES  
Latched W-R  
combined with  
nCMD  
nWR  
I/O Write strobe - asynchronous write access. Address is valid  
before leading edge . Data latched on trailing edge. Must not be  
active during DMA bursts if DMA is supported.  
nSTART  
nADS  
Address strobe is connected to EISA nSTART.  
RESDRV  
RESET  
nBE0 nBE1 nBE2  
nBE3  
nBE0 n BE1 nBE2  
nBE3  
Byte enables. Latched on nADS rising edge.  
Interrupts used as active high edge triggered  
IRQn  
INTR0  
D0-D31  
D0-D31  
32 bit data bus. The bus byte(s) used to access the device are a  
function of nBE0-nBE3:  
nBE0  
nBE1 nBE2 nBE3  
0
0
1
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
1
1
0
Double word access  
Low word access  
High word access  
Byte 0 access  
Byte 1 access  
Byte 2 access  
Byte 3 access  
Not used = tri-state on reads, ignored on writes. Note that nBE2 and  
nBE3 override the value of A1, which is tied low in this application.  
Other combinations of nBE are not supported by the LAN91C111.  
Software drivers are not anticipated to generate them.  
nEX32  
nLDEV  
nLDEV is a totem pole output. nLDEV is active on valid decodes of  
LAN91C111 pins A15-A4, and AEN=0. nNOWS is similar to nLDEV  
except that it should go inactive on nSTART rising. nNOWS can be  
used to request compressed cycles (1.5 BCLK long, nRD/nWR will  
be 1/2 BCLK wide).  
nNOWS  
(optional additional  
logic)  
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES  
BCLK  
LCLK  
EISA Bus Clock. Data transfer clock for DMA bursts.  
nDAK<n>  
nDATACS  
DMA Acknowledge. Active during Slave DMA cycles. Used by the  
LAN91C111 as nDATACS direct access to data path.  
nIORC  
W/nR  
Indicates the direction and timing of the DMA cycles. High during  
LAN91C111 writes, low during LAN91C111 reads.  
nIOWC  
nCYCLE  
Indicates slave DMA writes.  
nEXRDY  
nRDYRTN  
EISA bus signal indicating whether a slave DMA cycle will take place  
on the next BCLK rising edge, or should be postponed. nRDYRTN  
is used as an input in the slave DMA mode to bring in EXRDY.  
UNUSED PINS  
VCC  
nVLBUS  
A1  
GND  
Revision 1.8 (07-13-05)  
116  
SMSC LAN91C111-REV B  
DATASHEET  
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