10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
multicast packets that might not be for the node, and that are not subject to upper layer software flow
control.
INTERRUPT GENERATION
The interrupt strategy for the transmit and receive processes is such that it does not represent the
bottleneck in the transmit and receive queue management between the software driver and the
controller. For that purpose there is no register reading necessary before the next element in the
queue (namely transmit or receive packet) can be handled by the controller. The transmit and receive
results are placed in memory.
The receive interrupt will be generated when the receive queue (FIFO of packets) is not empty and
receive interrupts are enabled. This allows the interrupt service routine to process many receive
packets without exiting, or one at a time if the ISR just returns after processing and removing one.
There are two types of transmit interrupt strategies:
1. One interrupt per packet.
2. One interrupt per sequence of packets.
The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used.
TX INT bit - Set whenever the TX completion FIFO is not empty.
TX EMPTY INT bit - Set whenever the TX FIFO is empty.
AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and
their memory is released automatically.
1. One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the
completion result in memory and process the interrupt one packet at a time. Depending on the
completion code the driver will take different actions. Note that the transmit process is working in
parallel and other transmissions might be taking place. The LAN91C111 is virtually queuing the
packet numbers and their status words.
In this case, the transmit interrupt service routine can find the next packet number to be serviced by
reading the TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the
driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C111
and provided back to the CPU as their transmission completes.
2. One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO
RELEASE=1. TX EMPTY INT is generated only after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has
stopped and therefore the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that
when AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed
successfully.
Note: The pointer register is shared by any process accessing the LAN91C111 memory. In order to
allow processes to be interruptible, the interrupting process is responsible for reading the
pointer value before modifying it, saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1. Transmit loading (sometimes interrupt driven)
2. Receive unloading (interrupt driven)
3. Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the
PNR is also required from interrupt service routines.
Revision 1.8 (07-13-05)
104
SMSC LAN91C111-REV B
DATASHEET
SMSC [ SMSC CORPORATION ]
