10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
DRIVER SEND
ALLOCATE
Choose Bank Select
Register 2
Issue "Allocate Memory"
Command to MMU
Call ALLOCATE
Exit Driver Send
Read Interrupt Status Register
Ye s
No
Allocation
Passed?
Read Allocation Result
Register
Write Allocated Packet into
Packet # Register
Store Data Buffer Pointer
Clear "Ready for Packet" Flag
Enable Allocation Interrupt
Write Address Pointer Register
Copy Part of TX Data Packet
into RAM
Write Source Address into
Proper Location
Copy Remaining TX Data
Packet into RAM
Enqueue Packet
Set "Ready for Packet" Flag
Return Buffers to Upper Layer
Return
Figure 10.5 Drive Send and Allocate Routines
MEMORY PARTITIONING
Unlike other controllers, the LAN91C111 does not require a fixed memory partitioning between transmit
and receive resources. The MMU allocates and de-allocates memory upon different events. An
additional mechanism allows the CPU to prevent the receive process from starving the transmit
memory allocation.
Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the
MAC for receive. The CPU can control the number of bytes it requests for transmit but it cannot
determine the number of bytes the receive process is going to demand. Furthermore, the receive
process requests will be dependent on network traffic, in particular on the arrival of broadcast and
SMSC LAN91C111-REV B
103
Revision 1.8 (07-13-05)
DATASHEET
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