I/O SPACE - BANK2
OFFSET
NAME
TYPE
SYMBOL
IST
C
INTERRUPT STATUS REGISTER
READ ONLY
ERCV INT EPH INT RX_OVRN
INT
ALLOC
INT
TX
EMPTY
INT
TX INT
RCV INT
X
0
0
0
0
1
0
0
OFFSET
C
NAME
TYPE
WRITE ONLY
SYMBOL
ACK
INTERRUPT ACKNOWLEDGE
REGISTER
ERCV INT
RX_OVRN
INT
TX
EMPTY
INT
TX INT
OFFSET
D
NAME
TYPE
READ/WRITE
SYMBOL
MSK
INTERRUPT MASK REGISTER
ERCV INT EPH INT RX_OVRN
INT
ALLOC
INT
TX
EMPTY
INT
TX INT
RCV INT
X
0
0
0
0
0
0
0
This register can be read and written as a word
or as two individual bytes.
exceeds the value programmed as ERCV
THRESHOLD (Bank 3, Offset Ch). ERCV INT
stays set until acknowledged by writing the
INTERRUPT ACKNOWLEDGE REGISTER with
the ERCV INT bit set.
The Interrupt Mask Register bits enable the
appropriate bits when high and disable them
when low. An enabled bit being set will cause a
hardware interrupt.
EPH INT
Set when the Ethernet Protocol
Handler section indicates one out of various
possible special conditions. This bit merges
exception type of interrupt sources, whose
service time is not critical to the execution speed
ERCV INT
Early receive interrupt.
Set
whenever a receive packet is being received,
and the number of bytes received into memory
42
SMSC [ SMSC CORPORATION ]
