High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 5.6 LAN9117 MAC CSR Register Map
MAC CONTROL AND STATUS REGISTERS
INDEX
SYMBOL
REGISTER NAME
MAC Control Register
DEFAULT
00040000h
0000FFFFh
FFFFFFFFh
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
1
2
3
4
5
6
7
8
9
A
B
C
MAC_CR
ADDRH
ADDRL
HASHH
HASHL
MII_ACC
MII_DATA
FLOW
MAC Address High
MAC Address Low
Multicast Hash Table High
Multicast Hash Table Low
MII Access
MII Data
Flow Control
VLAN1
VLAN1 Tag
VLAN2
VLAN2 Tag
WUFF
Wake-up Frame Filter
Wake-up Control and Status
WUCSR
5.4.1
MAC_CR—MAC Control Register
Offset:
1
Attribute:
Size:
R/W
Default Value:
00040000h
32 bits
This register establishes the RX and TX operation modes and controls for address filtering and packet
filtering.
BITS
DESCRIPTION
31
Receive All Mode (RXALL). When set, all incoming packets will be received and passed on to the
address filtering Function for processing of the selected filtering mode on the received frame. Address
filtering then occurs and is reported in Receive Status. When reset, only frames that pass Destination
Address filtering will be sent to the Application.
30-24
23
Reserved
Disable Receive Own (RCVOWN). When set, the MAC disables the reception of frames when TXEN
is asserted. The MAC blocks the transmitted frame on the receive path. When reset, the MAC receives
all packets the PHY gives, including those transmitted by the MAC.This bit should be reset when the
Full Duplex Mode bit is set.
22
Reserved
SMSC LAN9117
Revision 1.1 (05-17-05)
DATA9S7HEET
SMSC [ SMSC CORPORATION ]
