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LAN9117-MT 参数 Datasheet PDF下载

LAN9117-MT图片预览
型号: LAN9117-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能单芯片10/100非PCI以太网控制器 [HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER]
分类和应用: 外围集成电路数据传输控制器PC局域网以太网局域网(LAN)标准以太网:16GBASE-T通信时钟
文件页数/大小: 131 页 / 1539 K
品牌: SMSC [ SMSC CORPORATION ]
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller  
Datasheet  
is loaded from address 0x05 of the EEPROM. The second byte (bits [15:8]) is loaded from address  
0x06 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM. Section 5.4.3  
details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the  
Ethernet physical address.  
BITS  
31-16  
15-0  
DESCRIPTION  
Reserved  
Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of  
the LAN9117 device. The content of this field is undefined until loaded from the EEPROM at power-  
on. The host can update the contents of this field after the initialization process has completed.  
5.4.3  
ADDRL—MAC Address Low Register  
Offset:  
3
Attribute:  
Size:  
R/W  
Default Value:  
FFFFFFFFh  
32 bits  
The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The  
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM  
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])  
is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from  
address 0x04 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM.  
BITS  
DESCRIPTION  
31-0  
Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the  
LAN9117 device. The content of this field is undefined until loaded from the EEPROM at power-on.  
The host can update the contents of this field after the initialization process has completed.  
Table 5.7 below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the  
reception of the Ethernet physical address. Also shown is the correlation between the EEPROM  
addresses and ADDRL and ADDRH registers.  
Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering  
ORDER OF RECEPTION ON  
EEPROM ADDRESS  
ADDRN  
ETHERNET  
st  
0x01  
0x02  
0x03  
0x04  
0x05  
0x06  
ADDRL[7:0]  
ADDRL[15:8]  
ADDRL[23:16]  
ADDRL[31:24]  
ADDRH[7:0]  
ADDRH[15:8]  
1
nd  
2
rd  
3
th  
4
th  
5
th  
6
Revision 1.1 (05-17-05)  
100  
SMSC LAN9117  
DATASHEET