High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
made in the RX data FIFO. For each frame of data that is lost, the RX Dropped Frames Counter
(RX_DROP) is incremented.
RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate
independent of the TX adatand RX data and status FIFOs. FIFO levels set for the RX and TX data
and Status FIFOs do not take into consideration the MIL FIFOs.
5.3.10
RX_DP_CTRL—Receive Datapath Control Register
Offset:
78h
Size:
32 bits
This register is used to discard unwanted receive frames.
BITS
DESCRIPTION
TYPE
DEFAULT
31
RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes
the RX data FIFO to fast-forward to the start of the next frame. This bit will
remain high until the RX data FIFO fast-forward operation has completed.
No reads should be issued to the RX data FIFO while this bit is high.
R/W
0h
Note:
Please refer to section “Receive Data FIFO Fast Forward” on
page 58 for detailed information regarding the use of RX_FFWD.
30-0
Reserved
RO
-
5.3.11
RX_FIFO_INF—Receive FIFO Information Register
Offset:
7Ch
Size:
32 bits
This register contains the used space in the receive FIFOs of the LAN9117 Ethernet Controller.
BITS
31-24
23-16
DESCRIPTION
Reserved
TYPE
RO
DEFAULT
-
RX Status FIFO Used Space (RXSUSED). Indicates the amount of space
RO
00h
in DWORDs, used in the RX Status FIFO.
15-0
RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in
bytes, used in the RX data FIFO. For each receive frame, this field is
incremented by the length of the receive data rounded up to the nearest
DWORD (if the payload does not end on a DWORD boundary).
RO
0000h
Revision 1.1 (05-17-05)
SMSC LAN9117
DATA8S4HEET
SMSC [ SMSC CORPORATION ]
