High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 5.8 LAN9117 PHY Control and Status Register (continued)
PHY CONTROL AND STATUS REGISTERS
INDEX
REGISTER NAME
(IN DECIMAL)
4
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Mode Control/Status Register
Special Modes Register
5
6
17
18
27
29
30
31
Special Control/Status Indications
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
5.5.1
Basic Control Register
Index (In Decimal):
0
Size:
16-bits
BITS
DESCRIPTION
TYPE
DEFAULT
15
Reset. 1 = software reset. Bit is self-clearing. For best results, when setting
RW/SC
0
this bit do not set other bits in this register.
14
13
Loopback. 1 = loopback mode, 0 = normal operation
RW
RW
0
Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is
See Note 5.2
enabled (0.12 = 1).
12
11
Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides
RW
RW
See Note 5.2
0
0.13 and 0.8) 0 = disable auto-negotiate process.
Power Down. 1 = General power down-mode, 0 = normal operation.
Note:
After this bit is cleared, the PHY may auto-negotiate with it's
partner station. This process may take a few seconds to complete.
Once auto-negotiation is complete, bit 5 of the PHY's Basic Status
Register will be set.
10
9
Reserved
RO
0
0
Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal
RW/SC
operation. Bit is self-clearing.
8
7
Duplex Mode. 1 = full duplex, 0 = half duplex. Ignored if Auto Negotiation
RW
RW
0
0
is enabled (0.12 = 1).
Collision Test. 1 = enable COL test, 0 = disable COL test
SMSC LAN9117
107
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
