High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.4.12
WUCSR—Wake-up Control and Status Register
Offset:
C
Attribute:
Size:
R/W
Default Value:
00000000h
32 bits
This register contains data pertaining to the MAC’s remote wake-up status and capabilities.
BITS
31-10
9
DESCRIPTION
Reserved
Global Unicast Enable (GUE). When set, the MAC wakes up from power-saving mode on receipt of
a global unicast frame. A global unicast frame has the MAC Address [1:0] bit set to 0.
8-7
6
Reserved
Remote Wake-Up Frame Received (WUFR). The MAC, upon receiving a valid Remote Wake-up
frame, sets this bit..
5
4-3
2
Magic Packet Received (MPR). Tthe MAC, upon receiving a valid Magic Packet, sets this bit.
Reserved
Wake-Up Frame enabled (WUEN). When set, Remote Wake-Up mode is enabled and the MAC is
capable of detecting wake-up frames as programmed in the wake-up frame filter.
1
0
Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled.
Reserved
5.5
PHY Registers
The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC
via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers.
PHY Register Indexes are shown in Table 5.8, "LAN9117 PHY Control and Status Register"below.
Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of
the PHY Basic Control Register (Reset) is set.
Table 5.8 LAN9117 PHY Control and Status Register
PHY CONTROL AND STATUS REGISTERS
INDEX
(IN DECIMAL)
REGISTER NAME
0
1
2
3
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
Revision 1.1 (05-17-05)
106
SMSC LAN9117
DATASHEET
SMSC [ SMSC CORPORATION ]
