Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
DESCRIPTION
TYPE
R/W
DEFAULT
3
PME indication (PME_IND). The PME signal can be configured as a pulsed
output or a static signal, which is asserted upon detection of a wake-up
event.
0b
When set, the PME signal will pulse active for 50mS upon detection of a
wake-up event.
When clear, the PME signal is driven continously upon detection of a wake-
up event.
The PME signal can be deactivated by clearing the WUPS bits, or by
clearing the appropriate enable (refer to Section 3.10.2.3, "Power
Managment Event Indicators," on page 39).
2
PME Polarity (PME_POL). This bit controls the polarity of the PME signal.
When set, the PME output is an active high signal. When reset, it is active
low. When PME is configured as an open-drain output this field is ignored,
and the output is always active low.
R/W
0b
NASR
1
0
PME Enable (PME_EN). When set, this bit enables the external PME signal.
R/W
RO
0b
-
This bit does not affect the PME interrupt (PME_INT).
Device Ready (READY). When set, this bit indicates that LAN9116 is ready
to be accessed. This register can be read when LAN9116 is in any power
management mode. Upon waking from any power management mode,
including power-up, the host processor can interrogate this field as an
indication when LAN9116 has stabilized and is fully alive. Reads and writes
of any other address are invalid until this bit is set.
Note:
With the exception of HW_CFG and PMT_CTRL, read access to
any internal resources is forbidden while the READY bit is cleared.
SMSC LAN9116
Revision 1.1 (05-17-05)
DATA8S1HEET
SMSC [ SMSC CORPORATION ]
