Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 2.3 LAN Interface Signals
PIN
NO.
BUFFER
TYPE
NUM
PINS
NAME
SYMBOL
DESCRIPTION
79
TXP
TPO+
AO
1
Twisted Pair Transmit Output,
Positive
78
TXN
TPO-
AO
1
Twisted Pair Transmit Output,
Negative
83
82
87
RXP
RXN
TPI+
TPI-
AI
AI
AI
1
1
1
Twisted Pair Receive Input, Positive
Twisted Pair Receive Input, Negative
PHY External Bias
Resistor
EXRES1
Must be connected to ground through
a 12.4K ohm 1% resistor.
Table 2.4 Serial EEPROM Interface Signals
PIN
NO.
BUFFER
TYPE
NUM
PINS
NAME
SYMBOL
DESCRIPTION
67
EEPROM Data,
GPO3, TX_EN,
TX_CLK,
EEDIO/GPO3/
TX_EN/TX_CLK
(D32/nD16)
I/O8
1
EEPROM Data: This bi-directional
pin can be connected to a serial
EEPROM DIO. This is optional.
D32/nD16
General Purpose Output 3: This
pin can also function as a general
purpose output, or it can be
configured to monitor the TX_EN or
TX_CLK signals on the internal MII
port. When configured as a GPO
signal, or as a TX_EN/TX_CLK
monitor, the EECS pin is deasserted
so as to never unintentionally access
the serial EEPROM. This signal
cannot function as a general-
purpose input.
Data Bus Width Select: This signal
also functions as a configuration
input on power-up and is used to
select the host bus data width. Upon
deassertion of reset, the value of the
input is latched. When high, a 32-bit
data bus is utilized. When low, a 16-
bit interface is utilized.
68
EEPROM Chip
Select
nEECS
O8
1
Serial EEPROM chip select.
Revision 1.1 (05-17-05)
SMSC LAN9116
DATA1S6HEET
SMSC [ SMSC CORPORATION ]
