Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.1 Read After Write Timing Rules
MINIMUM WAIT TIME FOR READ
FOLLOWING ANY WRITE CYCLE
(IN NS)
NUMBER OF BYTE_TEST
READS (ASSUMING TCYCLE OF
165NS)
REGISTER NAME
ID_REV
IRQ_CFG
0
0
3
2
1
0
1
1
1
1
1
0
3
7
1
1
3
1
4
0
1
1
1
1
1
495
330
165
0
INT_STS
INT_EN
BYTE_TEST
FIFO_INT
165
165
165
165
165
0
RX_CFG
TX_CFG
HW_CFG
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
PMT_CTRL
GPIO_CFG
GPT_CFG
GPT_CNT
495
1155
165
165
495
165
660
0
ENDIAN
FREE_RUN
RX_DROP
MAC_CSR_CMD
MAC_CSR_DATA
AFC_CFG
165
165
165
165
165
E2P_CMD
E2P_DATA
6.1.2
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9116, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in Table 6.2, "Read After Read Timing Rules". The host
SMSC LAN9116
111
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
