Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
1.1
Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal
Block Diagram".
25MHz
EEPROM
(Optional)
+3.3V
EEPROM
Controller
3.3V to 1.8V
Regulator
PME
PLL
Wakup Indicator
Power Management
2kB to 14kB
Host Bus Interface
(HBI)
Configurable TX FIFO
SRAM I/F
TX Status FIFO
RX Status FIFO
10/100
10/100
Ethernet
PHY
PIO Controller
LAN
Ethernet
MAC
IRQ
Interrupt
MIL - RX Elastic
Buffer - 128 bytes
Controller
FIFO_SEL
2kB to 14kB
Configurable RX FIFO
MIL - TX Elastic
Buffer - 2K bytes
GP Timer
Figure 1.2 Internal Block Diagram
1.2
1.3
10/100 Ethernet PHY
The LAN9116 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in
either full or half duplex configurations. The PHY block includes auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance
especially in full duplex mode. The data paths connect to the PIO interface Function via separate
busses to increase performance. Payload data as well as transmit and receive status is passed on
these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is
accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media
Independent Interface) port internal to the LAN9116. The MAC CSR's also provides a mechanism for
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly
accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and
the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer
can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working
SMSC LAN9116
11
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
