Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
6.6
PIO Writes
PIO writes are used for all LAN9116 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are
identical with the exception that D[31:16] are ignored during a 16-bit write.
nCS, nRD
Data Bus
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Table 6.7 PIO Write Cycle Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Write Cycle Time
165
32
13
0
ns
ns
ns
ns
ns
ns
ns
cycle
t
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
csl
t
csh
asu
t
t
0
ah
t
Data Setup to nCS, nWR Deassertion
Data Hold Time
7
dsu
t
0
dh
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
SMSC LAN9116
117
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
