Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Table 6.5 RX Data FIFO Direct PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Read Cycle Time
165
32
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
t
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
csl
t
13
csh
t
30
7
csdv
t
0
0
0
asu
t
ah
t
don
t
doff
doh
t
0
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
6.5
RX Data FIFO Direct PIO Burst Reads
In this mode the upper address inputs are not decoded, and any burst read of the LAN9116 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9116. Timing
SMSC LAN9116
115
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
