欢迎访问ic37.com |
会员登录 免费注册
发布采购

LAN8720I 参数 Datasheet PDF下载

LAN8720I图片预览
型号: LAN8720I
PDF下载: 下载PDF文件 查看货源
内容描述: 小尺寸RMII 10/100以太网收发器, HP Auto-MDIX的支持 [Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 79 页 / 1414 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LAN8720I的Datasheet PDF文件第21页浏览型号LAN8720I的Datasheet PDF文件第22页浏览型号LAN8720I的Datasheet PDF文件第23页浏览型号LAN8720I的Datasheet PDF文件第24页浏览型号LAN8720I的Datasheet PDF文件第26页浏览型号LAN8720I的Datasheet PDF文件第27页浏览型号LAN8720I的Datasheet PDF文件第28页浏览型号LAN8720I的Datasheet PDF文件第29页  
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support  
Datasheet  
4.5.3  
10M Receive Data Across the MII/RMII Interface  
For MII, the 4 bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on  
the rising edge of the 2.5 MHz RXCLK.  
For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid  
on the rising edge of the RMII REF_CLK.  
4.5.4  
Jabber Detection  
Jabber is a condition in which a station transmits for a period of time longer than the maximum  
permissible packet length, usually due to a fault condition, that results in holding the TXEN input for a  
long period. Special logic is used to detect the jabber state and abort the transmission to the line, within  
45ms. Once TXEN is deasserted, the logic resets the jabber condition.  
As shown in Table 5.22, bit 1.1 indicates that a jabber condition was detected.  
4.6  
MAC Interface  
The RMII block is responsible for the communication with the controller.  
4.6.1  
RMII  
The SMSC LAN8720 supports the low pin count Reduced Media Independent Interface (RMII)  
intended for use between Ethernet transceivers and Switch ASICs. Under IEEE 802.3, an MII  
comprised of 16 pins for data and control is defined. In devices incorporating many MACs or  
transceiver interfaces such as switches, the number of pins can add significant cost as the port counts  
increase. The management interface (MDIO/MDC) is identical to MII. The RMII interface has the  
following characteristics:  
„
„
„
„
It is capable of supporting 10Mb/s and 100Mb/s data rates  
A single clock reference is used for both transmit and receive.  
It provides independent 2 bit wide (di-bit) transmit and receive data paths  
It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes  
The RMII includes 6 interface signals with one of the signals being optional:  
„
„
„
„
„
„
transmit data - TXD[1:0]  
transmit strobe - TXEN  
receive data - RXD[1:0]  
receive error - RXER (Optional)  
carrier sense - CRS_DV  
Reference Clock - (RMII references usually define this signal as REF_CLK)  
4.6.1.1  
CRS_DV - Carrier Sense/Receive Data Valid  
The CRS_DV is asserted by the LAN8720/LAN8720i when the receive medium is non-idle. CRS_DV  
is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode.  
That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous  
zeroes in 10 bits are detected, carrier is said to be detected.  
Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which  
presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble  
boundaries). If the LAN8720/LAN8720i has additional bits to be presented on RXD[1:0] following the  
initial deassertion of CRS_DV, then the LAN8720/LAN8720i shall assert CRS_DV on cycles of  
REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of  
REF_CLK which present the first di-bit of a nibble. The result is: Starting on nibble boundaries  
SMSC LAN8720/LAN8720i  
Revision 1.0 (05-28-09)  
DATA2S5HEET