®
MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology in a Small Footprint
Datasheet
5.3.5.1
5.3.5.2
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the entire transceiver, except the
management interface, is powered-down and stays in that condition as long as bit 0.11 is HIGH. When
bit 0.11 is cleared, the transceiver powers up and is automatically reset.
Energy Detect Power-Down
This power-down mode is activated by setting bit 17.13 to 1. In this mode when no energy is present
on the line the transceiver is powered down, except for the management interface, the SQUELCH
circuit and the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy
from 100Base-TX, 10Base-T, or Auto-negotiation signals
In this mode, when the ENERGYON signal is low, the transceiver is powered-down, and nothing is
transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and
the transceiver powers-up. It automatically resets itself into the state it had prior to power-down, and
asserts the nINT interrupt if the ENERGYON interrupt is enabled. The first and possibly the second
packet to activate ENERGYON may be lost.
When 17.13 is low, energy detect power-down is disabled.
5.3.6
Reset
The LAN8710 registers are reset by the Hardware and Software resets. Some SMI register bits are
not cleared by Software reset, and these are marked “NASR” in the register tables. The SMI registers
are not reset by the power-down modes described in Section 5.3.5.
For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25
MHz if auto-negotiation is enabled.
5.3.6.1
5.3.6.2
5.3.7
Hardware Reset
Hardware reset is asserted by driving the nRST input low.
When the nRST input is driven by an external source, it should be held LOW for at least 100 us to
ensure that the transceiver is properly reset. During a hardware reset an external clock must be
supplied to the XTAL1/CLKIN signal.
Software Reset
Software reset is activated by writing register 0, bit 15 high. This signal is self- clearing. The SMI
registers are reset except those that are marked “NASR” in the register tables.
The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed
within 0.5s from the setting of this bit.
LED Description
The LAN8710 provides two LED signals. These provide a convenient means to determine the mode
of operation of the transceiver. All LED signals are either active high or active low as described in
Section 4.10 and Section 4.11.
The LED1 output is driven active whenever the LAN8710 detects a valid link, and blinks when CRS is
active (high) indicating activity.
The LED2 output is driven active when the operating speed is 100Mbit/s. This LED will go inactive
when the operating speed is 10Mbit/s or during line isolation (register 31 bit 5).
5.3.8
Loopback Operation
The LAN8710 may be configured for near-end loopback and far loopback.
Revision 1.0 (04-15-09)
SMSC LAN8710/LAN8710i
DATA5S0HEET
SMSC [ SMSC CORPORATION ]
