®
MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology in a Small Footprint
Datasheet
4.5.3
4.5.4
10M Receive Data Across the MII/RMII Interface
For MII, the 4 bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on
the rising edge of the 2.5 MHz RXCLK.
For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid
on the rising edge of the RMII REF_CLK.
Jabber Detection
Jabber is a condition in which a station transmits for a period of time longer than the maximum
permissible packet length, usually due to a fault condition, that results in holding the TXEN input for a
long period. Special logic is used to detect the jabber state and abort the transmission to the line, within
45ms. Once TXEN is deasserted, the logic resets the jabber condition.
As shown in Table 5.22, bit 1.1 indicates that a jabber condition was detected.
4.6
MAC Interface
The MII/RMII block is responsible for the communication with the controller. Special sets of hand-shake
signals are used to indicate that valid received/transmitted data is present on the 4 bit receive/transmit
bus.
The device must be configured in MII or RMII mode. This is done by specific pin strapping
configurations.
See Section 4.6.3, "MII vs. RMII Configuration," on page 27 for information on pin strapping and how
the pins are mapped differently.
4.6.1
MII
The MII includes 16 interface signals:
transmit data - TXD[3:0]
transmit strobe - TXEN
transmit clock - TXCLK
transmit error - TXER/TXD4
receive data - RXD[3:0]
receive strobe - RXDV
receive clock - RXCLK
receive error - RXER/RXD4/PHYAD0
collision indication - COL
carrier sense - CRS
In MII mode, on the transmit path, the transceiver drives the transmit clock, TXCLK, to the controller.
The controller synchronizes the transmit data to the rising edge of TXCLK. The controller drives TXEN
high to indicate valid transmit data. The controller drives TXER high when a transmit error is detected.
On the receive path, the transceiver drives both the receive data, RXD[3:0], and the RXCLK signal.
The controller clocks in the receive data on the rising edge of RXCLK when the transceiver drives
RXDV high. The transceiver drives RXER high when a receive error is detected.
4.6.2
RMII
The SMSC LAN8710 supports the low pin count Reduced Media Independent Interface (RMII)
intended for use between Ethernet transceivers and Switch ASICs. Under IEEE 802.3, an MII
Revision 1.0 (04-15-09)
SMSC LAN8710/LAN8710i
DATA2S6HEET
SMSC [ SMSC CORPORATION ]
