Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
5.5.3
Power-On nRST & Configuration Strap Timing
This diagram illustrates the nRST reset and configuration strap timing requirements in relation to
power-on. A hardware reset (nRST assertion) is required following power-up. For proper operation,
nRST must be asserted for no less than trstia. The nRST pin can be asserted at any time, but must
not be deasserted before tpurstd after all external power supplies have reached 80% of their nominal
operating levels. In order for valid configuration strap values to be read at power-up, the tcss and tcsh
timing constraints must be followed. Refer to Section 3.8.5, "Resets," on page 41 for additional
information.
All External
Power Supplies
80%
tpurstd
tpurstv
trstia
nRST
tcss
tcsh
Configuration Strap
Pins Input
totaa
todad
Configuration Strap
Pins Output Drive
Figure 5.3 Power-On nRST & Configuration Strap Timing
Table 5.7 Power-On nRST & Configuration Strap Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tpurstd
tpurstv
trstia
tcss
External power supplies at 80% to nRST deassertion
External power supplies at 80% to nRST valid
nRST input assertion time
25
0
mS
nS
μS
nS
nS
nS
nS
100
200
1
Configuration strap pins setup to nRST deassertion
Configuration strap pins hold after nRST deassertion
Output tri-state after nRST assertion
tcsh
totaa
todad
50
Output drive after nRST deassertion
2
800
(Note 5.14)
Note: nRST deassertion must be monotonic.
Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7,
"Configuration Straps," on page 36 for details. Configuration straps must only be pulled high or
low and must not be driven as inputs.
Note 5.14 20 clock cycles for 25MHz, or 40 clock cycles for 50MHz.
Revision 1.4 (08-23-12)
72
SMSC LAN8710A/LAN8710Ai
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