欢迎访问ic37.com |
会员登录 免费注册
发布采购

LAN8710AI 参数 Datasheet PDF下载

LAN8710AI图片预览
型号: LAN8710AI
PDF下载: 下载PDF文件 查看货源
内容描述: 小尺寸MII / RMII 10/100以太网收发器, HP Auto-MDIX的和flexPWR技术 [Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 82 页 / 1172 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LAN8710AI的Datasheet PDF文件第64页浏览型号LAN8710AI的Datasheet PDF文件第65页浏览型号LAN8710AI的Datasheet PDF文件第66页浏览型号LAN8710AI的Datasheet PDF文件第67页浏览型号LAN8710AI的Datasheet PDF文件第69页浏览型号LAN8710AI的Datasheet PDF文件第70页浏览型号LAN8710AI的Datasheet PDF文件第71页浏览型号LAN8710AI的Datasheet PDF文件第72页  
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology  
Datasheet  
Note: Current measurements do not include power applied to the magnetics or the optional external  
LEDs. The Ethernet component current is typically 41mA in 100BASE-TX mode and 100mA in  
10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer.  
Note 5.6 Calculated with full flexPWR features activated: VDDIO=1.8V & internal regulator disabled.  
5.4  
DC Specifications  
Table 5.2 details the non-variable I/O buffer characteristics. These buffer types do not support variable  
voltage operation. Table 5.3 details the variable voltage I/O buffer characteristics. Typical values are  
provided for 1.8V, 2.5V, and 3.3V VDDIO cases.  
Table 5.2 Non-Variable I/O Buffer Characteristics  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
IS Type Input Buffer  
Low Input Level  
VILI  
VIHI  
-0.3  
V
V
High Input Level  
3.6  
1.39  
1.79  
459  
Negative-Going Threshold  
Positive-Going Threshold  
Schmitt Trigger Hysteresis  
VILT  
VIHT  
VHYS  
1.01  
1.39  
336  
1.19  
1.59  
399  
V
Schmitt trigger  
Schmitt trigger  
V
mV  
(VIHT - VILT  
)
Input Leakage  
IIH  
-10  
10  
2
uA  
pF  
Note 5.7  
(VIN = VSS or VDDIO)  
Input Capacitance  
O12 Type Buffers  
CIN  
Low Output Level  
High Output Level  
VOL  
VOH  
0.4  
V
V
IOL = 12mA  
VDD2A - 0.4  
IOH = -12mA  
Note 5.8  
ICLK Type Buffer  
(XTAL1 Input)  
Low Input Level  
High Input Level  
VILI  
VIHI  
-0.3  
1.4  
0.35  
V
V
VDD2A + 0.4  
Note 5.7 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down  
and pull-up resistors add +/- 50uA per-pin (typical).  
Note 5.8 XTAL1/CLKIN can optionally be driven from a 25MHz single-ended clock oscillator.  
Revision 1.4 (08-23-12)  
68  
SMSC LAN8710A/LAN8710Ai  
DATASHEET