®
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology
Datasheet
3.5
Serial Management Interface (SMI)
The Serial Management Interface is used to control the device and obtain its status. This interface
supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-
specific” registers 16 to 31 allowed by the specification. Non-supported registers (such as 7 to 15) will
be read as hexadecimal “FFFF”. Device registers are detailed in Chapter 4, "Register Descriptions,"
on page 50.
At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock
provided by the station management controller (SMC). MDIO is a bi-directional data SMI input/output
signal that receives serial data (commands) from the controller SMC and sends serial data (status) to
the SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time
between edges. The minimum cycle time (time between two consecutive rising or two consecutive
falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by
the I/O port of a microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in Figure 3.5 and Figure 3.6. The timing relationships of the MDIO signals are
further described in Section 5.5.6, "SMI Timing," on page 76.
Read Cycle
MDC
...
D1
D15 D14
D0
32 1's
0
1
1
0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
...
MDIO
Start of
Frame
OP
Code
Turn
Around
Preamble
PHY Address
Register Address
Data
Data To Phy
Data From Phy
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle
Write Cycle
MDC
...
D15 D14
D1
D0
32 1's
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHY Address Register Address
...
MDIO
Start of
Frame
OP
Code
Turn
Around
Preamble
Data
Data To Phy
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle
SMSC LAN8710A/LAN8710Ai
33
Revision 1.4 (08-23-12)
DATASHEET
SMSC [ SMSC CORPORATION ]
