FUNCTIONAL DESCRIPTION
The LAN83C180 has three basic operating modes: 10BASE-T mode, 100BASE-TX mode and LOW-POWER mode.
The modes are selected by bits 11 and 13 respectively in register 0. The Control block is designed to manage these
modes by starting and stopping the two transceivers in a well-controlled manner such that no spurious signals are
output on either the MII or twisted-pair interfaces. Furthermore, it continuously monitors the behavior of the
transceivers and takes corrective action if a fault is detected.
Other modes described herein are repeater mode and reset mode.
25MHz Reference Clock
The LAN83C180 requires a 25MHz +/-100ppm timing reference for 802.3 compatible operation. This may be
supplied either from the integrated oscillator or from an external source. When the integrated oscillator is used, a
suitable crystal must be connected across the XTAL1 & XTAL2 pins (see “External Components”). When an external
source is used, it must be input to the REFCLK pin and XTAL1 must be tied high. XTAL2 must be unconnected.
10BASE-T OPERATION
10Mb/s Data Transfer on the MII
10Mb/s data is transferred across the MII with clock speeds of 2.5MHz. The MAC outputs data to the LAN83C180 via
the MII interface, on the TXD[3:0] bus. This data is synchronized to the rising edge of TX_CLK. To indicate that there
is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the LAN83C180 device
to take in the data on the TXD[3:0] bus. This is serialized and directly encoded as Manchester data, before being
output on the TXOP/TXON differential output for transmission through 1:1 magnetics and onto the twisted-pair. The
Pulse Shaper & Filter employs a digital finite impulse response filter (FIR) to pre-compensate for line distortion and
to remove high frequency components in accordance with the 802.3 Standard. The transmit current is governed by
the current through the TXREF10 pin, which must be grounded through a resistor as described in “External
Components”.
If TX_ER is active while TX_EN is high, then the LAN83C180 will transmit the illegal codes JKJK (00 11 00 11) on
the serial data out. This ensures that errors are propagated to the link partner.
RX10 Clock Recovery
The LAN83C180 employs a digital delay line controlled by the 100MHz Synthesizer DLL to derive a sampling clock
from the incoming signal. The recovered clock runs at twice the data rate (nominally 20MHz). When a signal is
received from the Signal Detect block, it is used to strobe Link Pulses and Manchester encoded serial data.
The Manchester data stream will be decoded into a 4-bit parallel data bus, RXD[3:0]. The RXD bus is clocked out on
RX_CLK rising. The LAN83C180 must detect the first 4 bits of preamble before RX_DV is set high. When RX_DV is
high, any Manchester coding violation will set RX_ER high. RX_DV is reset by a continuous sequence of zeroes, or
by the end-of-packet IDLE terminator (11 11 00 00). While RX_DV is low, the data on the receive nibble is always
5h.
100MHz Synthesizer
This synthesizer employs a delay-locked loop (DLL) to generate a 100MHz timing reference from the 25MHz
reference clock. This 100MHz reference is used by the 10BASE-T transmit and receive functions and is divided by 5
to provide a 20MHz data strobe. The 20MHz clock is used to derive the 2.5 MHz TX_CLK in 10BASE-T mode. The
synthesizer is disabled when not in 10BASE-T mode.
TX10 Pulse Shaper & Filter
The Pulse Shaper & Filter employs a digital finite impulse response filter (FIR) to pre-compensate for line distortion
and to remove high frequency components in accordance with the 802.3 Standard. The Pulse Shaper & Filter is
disabled when not in 10BASE-T mode.
TX10 Latency
When connected to appropriate magnetics the latency through the TX10 path is less than 2BT (200ns) for data
transmissions. This timing is measured from the falling edge of TX_CLK to the output of the transmit magnetics. The
TX10 path will not transmit the first two Manchester encoded bits of a data transmission, as permitted by the 802.3
Standard.
RX10 Filter & RX10 Signal Detect
These blocks work in unison to remove noise and to block signals that do not achieve the voltage levels specified in
802.3. Signals that do not achieve the required level are not sampled in the Clock Recovery block and are not
passed to the outputs.
SMSC DS – LAN83C180
Page 7
Rev. 08/24/2001
SMSC [ SMSC CORPORATION ]
