DESCRIPTION OF PIN FUNCTIONS
PIN NO.
72:79
41:52
53
70
90
80
67:61,
59:54
82,84,
86,88
81,83,
85,87
89
68
69
35
36
22
37
38
39
21, 60,
101, 125,
139
32
1, 8, 40,
71, 95,
123, 130
17
12
System Data Bus
System Address Bus
Chip Select/SA12 (Active Low)(Note 1, 4)
Address Enable (DMA master has bus control)
I/O Channel Ready
Reset Drive
Interrupt Requests [1,3:12,14,15]
(Polarity control for IRQ8)
DMA Requests
DMA Acknowledge
Terminal Count
I/O Read
I/O Write
High Speed Clock Out 24/48 MHz
16 MHz Out
14.318 MHz Clock Input
14.318 MHz Clock Output 1
14.318 MHz Clock Output 2
14.318 MHz Clock Output 3
POWER PINS
+5V Supply Voltage
VCC
NAME
PROCESSOR/HOST INTERFACE
SD[0:7]
SA[0:11]
nCS
AEN
IOCHRDY
RESET_DRV
IRQ[1,3:12,
14,15]
DRQ[0:3]
nDACK[0:3]
TC
nIOR
nIOW
HCLK
16CLK
CLOCKI
CLKO1
CLKO2
CLKO3
I/O24
I
I
I
OD24
IS
024/OD24
(Note 0)
O24
I
I
I
I
O20
O8SR
ICLK
O16SR
O8SR
O8SR
SYMBOL
BUFFER TYPE
Trickle Voltage Input
Ground
VTR
GND
FDD INTERFACE
Read Disk Data
Write Gate
nRDATA
nWGATE
IS
OD48
5
SMSC [ SMSC CORPORATION ]
