DESCRIPTION OF PIN FUNCTIONS
PIN NO.
NAME
SYMBOL
BUFFER TYPE
PROCESSOR/HOST INTERFACE
72:79
41:52
53
System Data Bus
SD[0:7]
I/O24
System Address Bus
SA[0:11]
nCS
I
Chip Select/SA12 (Active Low)(Note 1, 4)
Address Enable (DMA master has bus control)
I/O Channel Ready
I
I
70
AEN
90
IOCHRDY
RESET_DRV
OD24
IS
80
Reset Drive
67:61,
59:54
Interrupt Requests [1,3:12,14,15]
(Polarity control for IRQ8)
IRQ[1,3:12,
14,15]
024/OD24
(Note 0)
82,84,
86,88
DMA Requests
DRQ[0:3]
O24
81,83,
85,87
DMA Acknowledge
nDACK[0:3]
I
89
68
69
35
36
22
37
38
39
Terminal Count
TC
I
I/O Read
nIOR
I
I/O Write
nIOW
HCLK
16CLK
CLOCKI
CLKO1
CLKO2
CLKO3
I
High Speed Clock Out 24/48 MHz
16 MHz Out
O20
O8SR
ICLK
O16SR
O8SR
O8SR
14.318 MHz Clock Input
14.318 MHz Clock Output 1
14.318 MHz Clock Output 2
14.318 MHz Clock Output 3
POWER PINS
21, 60,
101, 125,
139
+5V Supply Voltage
VCC
32
Trickle Voltage Input
VTR
1, 8, 40, Ground
71, 95,
GND
123, 130
FDD INTERFACE
17
12
Read Disk Data
Write Gate
nRDATA
nWGATE
IS
OD48
5
SMSC [ SMSC CORPORATION ]
