also contains the enable for the DMA logic and a
software reset bit. The contents of the DOR are
unaffected by a software reset. The DOR can
be written to at any time.
DIGITAL OUTPUT REGISTER (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor
enables of the disk interface outputs. It
7
6
5
4
3
2
1
0
MOT
EN3
MOT
EN2
MOT
EN1
MOT DMAEN nRESE DRIVE DRIVE
EN0
T
SEL1
SEL0
RESET
COND.
0
0
0
0
0
0
0
0
BIT 0 and 1 DRIVE SELECT
BIT 4 MOTOR ENABLE 0
These two bits are binary encoded for the four
drive selects DS0 -DS3, thereby allowing only
one drive to be selected at one time.
This bit controls the MTR0 disk interface output.
A logic "1" in this bit will cause the output pin to
go active.
BIT 2 nRESET
BIT 5 MOTOR ENABLE 1
A logic "0" written to this bit resets the Floppy
disk controller. This reset will remain active
until a logic "1" is written to this bit. This
software reset does not affect the DSR and CCR
registers, nor does it affect the other bits of the
DOR register. The minimum reset duration
required is 100ns, therefore toggling this bit by
consecutive writes to this register is a valid
method of issuing a software reset.
This bit controls the MTR1 disk interface output.
A logic "1" in this bit will cause the output pin to
go active.
BIT 6 MOTOR ENABLE 2
This bit controls the MTR2 disk interface output.
A logic "1" in this bit will cause the output pin to
go active.
BIT 7 MOTOR ENABLE 3
BIT 3 DMAEN
This bit controls the MTR3 disk interface output.
A logic "1" in this bit causes the output to go
active.
PC/AT and Model 30 Mode: Writing this bit to
logic "1" will enable the DRQ, nDACK, TC and
FINTR outputs. When this bit is a logic "0" it
disables the nDACK and TC inputs, and holds
Table 4 - Drive Activation Values
the DRQ and FINTR outputs in
impedance state. This bit is a logic "0" after a
reset and in these modes.
a high
DRIVE
DOR VALUE
0
1
2
3
1CH
2DH
4EH
8FH
PS/2 Mode: In this mode the DRQ, nDACK, TC
and FINTR pins are always enabled. During a
reset, the DRQ, nDACK, TC, and FINTR pins
will remain enabled, but this bit will be cleared to
a logic "0".
20
SMSC [ SMSC CORPORATION ]
